Recent hardware is generally constituted by a plurality of clock domains (clock domain: synchronous circuit domain operating with a specific clock signal or a clock signal obtained by dividing the frequency of the specific clock signal) and, thus, a verification of a mechanism of CDC (Clock Domain Crossing) between different clock domains becomes important. As an effective technique for verifying the CDC, simulation (CDC simulation) in which influence of the CDC is modeled in a logic level has now gotten attention.
FIG. 14A shows an arrangement example of clock domains, and FIG. 14B shows output timings of respective signals in the arrangement of FIG. 14A as a timing chart in which time is plotted on the horizontal axis. It is assumed that clock signals CLK1 and CLK2 have clock sources independent of each other. At the design stage of RTL (Register Transfer Level), it is impossible to estimate in which order and at which timing signal changes of A1 and B1 reach the clock domain 2. Further, the CLK1 and CLK2 are input to the clock domain 1 and clock domain 2 at different timings, so that it is unavoidable for the signal change to undergo Setup Time violation/Hold Time violation. In the configuration shown in FIGS. 14A and 14B, the output timing of the signal B2 becomes non-deterministic (random) which is called a meta-stable state.
Another arrangement example of clock domains will be described with reference to FIGS. 15A and 15B. In the example of FIG. 15A, a non-predictable operation is caused in the entire reception domain by the meta-stable state as in the above case. A 2FF synchronizer (FF: Flip Flop) in which two CLK2 having the same clock source is received by two stages is constructed as shown in FIG. 15B in order to eliminate the meta-stable state, whereby a stable logic value can be obtained. However, even in this arrangement, signal input timing is shifted by one cycle, resulting in a cycle-based random timing variation, i.e., CDC jitter.
In the case where the CDC jitter exits as described above, the following trouble may occur in a circuit configuration, as exemplified by FIG. 16, that receives a DATA signal at the output timing of a Valid signal. That is, although a transmission side has sent DATA=1 at the timing of Valid=1, a reception side falsely recognizes that DATA=0 has been sent due to the influence of the CDC jitter.
While whether a specification violation occurs in the output of DUT (Design Under Test (test target)) is checked in an RTL simulation, an additional special simulation method considering the CDC jitter is required in order to detect a failure caused by the CDC jitter when a verification is made for a circuit configuration of the DUT using simulation.
An example of a conventional CDC simulation method will be described with reference to FIGS. 17A and 17B. In the case of a circuit configuration in which a signal q2 is output based on two clock signals having different clock sources as shown in FIG. 17A, in order to achieve a circuit configuration considering the CDC jitter in this simulation, the circuit configuration of FIG. 17B is employed to execute the simulation.
That is, in the conventional CDC simulation, a selector that determines whether to output a signal s using a signal based on a jitter_R1 signal which is a random value (0 or 1) and an in_phase signal for checking a difference in the clock timing is built into an actual test circuit and then simulation is executed.
With reference to a flowchart of FIG. 18, the conventional simulation method will be further described below.
A conventional simulation apparatus executes a normal logic simulation (RTL simulation) for the DUT (S101). In the case where any error concerning the circuit arrangement has been detected (Yes in S102), a circuit modification is made (S109), and the flow returns to S101. On the other hand, in the case where no error has been detected (No in S102), it is determined whether a coverage criteria such as a line coverage is satisfied (S103). In the case where a coverage criteria is not satisfied (coverage is insufficient), (Yes in S103), an input pattern is added (S108), and the flow returns to S101.
In the case where a coverage criteria is satisfied (No in S103), the configuration shown in FIG. 17B is employed to execute the CDC simulation (S104). In the case where a result of the CDC simulation is error (Yes in S105), the circuit modification is made (S109). In the case where no error has been detected (No in S105), it is determined whether a coverage criteria is satisfied. In the case where a coverage criteria is satisfied (coverage is sufficient) (No in S106), the simulation is ended.
On the other hand, in the case where a coverage criteria is not satisfied (coverage is insufficient) (Yes in S106), a random number sequence in the CDC simulation is changed (S107), and the CDC simulation processing is executed once again (S104). There may be a case where a re-examination of the input pattern is required depending on circumstances (Yes in S106 to 3108).
As conventional technique relating to the present invention, the following documents have been disclosed.
[Patent Document 1]
Japanese Laid-open Patent Publication No. 2005-284426
[Patent Document 2]
Japanese Laid-open Patent Publication No. 2003-233638
[Patent Document 3]
Japanese Laid-open Patent Publication No. 2001-229211
[Non-Patent Document 1]
T. Ly, N. Hand, and C. K. Kwok, “Formally Verifying Clock Domain Crossing Jitter Using Assertion-Based Verification,” in Proc. Design and Verification Conference and Exhibition, 2004.
[Non-Patent Document 2]
M. Litterick, “Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions,” in Proc. Design and Verification Conference and Exhibition, 2006.
In the CDC simulation, random influence such as a cycle-based timing variation or pulse disappearance/pulse generation in a reception register is exerted on the signal change propagation from a given clock domain to another clock domain. This is achieved by replacing the value of the reception register by a random value during a certain period of time during which it is determined (determination differs depending on a determination method) to be influenced by the CDC as described above.
However, many logical troubles appear in association with a change in a plurality of respective CDC signals or a plurality of changes in the same CDC signal.
For example, in a circuit shown in FIG. 19A, a signal change does not appear in an observation point F in an RTL simulation result (see the left side of FIG. 19B). However, in the case where the RTL+CDC model simulation considering the CDC jitter is executed, there may exist a pattern by which any signal change occurs in the observation point F depending on the input timing of clock signals S4, S5, and S6 in FIG. 19 (see the right side of FIG. 19B).
In order to detect presence/absence of a signal change in the observation point F in the conventional CDC simulation, it is preferably to execute CDC simulation processing in 2n ways (in the example of FIG. 19, n=3(S4, S5, and S6), i.e., 23=8 patterns) for one simulation pattern. That is, 2n patterns are generated for the processing from step S106 to S107 and, accordingly, the CDC simulation processing (S104) needs to be executed in 2n ways. Further, there may be a case where a signal change does not appear in the observation point in spite of execution of all the patterns. Therefore, execution of the CDC simulation may result in vain.
Along with a recent increase in complexity and stage number of a circuit, there arises a need to execute the CDC simulation an enormous number of times for one simulation pattern, causing an increase in verification cost and decrease in verification quality.